In reply to Marc43:
You can use post_randomize() to create a state machine. I think you need three states
typedef enum {INIT,ONCE, DONE} fsm_t;
class foo;
fsm_t fsm = INIT;
rand int a;
constraint c_fsm {
fsm == ONCE -> a != 0;
}
function void poet_randomize ();
if (fsm == INIT && a == 1) fsm = ONCE;
if (done == 1) fsm == DONE;
endfunction
endclass
Hi, Dave, thank you for your reply :)
I see your point, but considering that “done” is an output this is also possible? I guess it is, but maybe for a UVM environment would be ugly and philosophy breaking?
Sorry for not indicating that I was using UVM. I did want to see if there was any solution without UVM.
Okay, I read the paper and seen the example. I see that for the probe interface do you use the port fashion, in UVM I have only seen class members, so I was wondering, it would be possible to use class members for the signals that I don’t want to probe (I will stimulate them in the driver with the sequences) and the ports of the interface for the signals I want to probe?
In reply to dave_59:
Thank you, Dave, for your response.
Sorry for not indicating that I was using UVM. I did want to see if there was any solution without UVM.
Okay, I read the paper and seen the example. I see that for the probe interface do you use the port fashion, in UVM I have only seen class members, so I was wondering, it would be possible to use class members for the signals that I don’t want to probe (I will stimulate them in the driver with the sequences) and the ports of the interface for the signals I want to probe?
Okay I see, in a certain way you do this.
But, how are you using create_object? I guess you use it because the factory can’t find the registered type and you are not able to do something like probe::type_id::create(…). Using create_object I have this error:
The name ('create_object') was not found in the current scope. Please verify the spelling of the name 'create_object'.
Great to have you in the forums Dave, thank you very much.