Constrain sum of elements in an array

SystemVerilog
, ,
18

In reply to muneebullashariff:

I am not seeing any constraint conflicts. I changed the code a little, as below


module tb;
 
class sum_array;
   rand int unsigned arr[];
 
   constraint arr_c { arr.size() == 4;
                      foreach(arr[i]) { (arr[i]%8) == 0; } }
 
   constraint sum_c { arr.sum() with (36'(item)) == 36'h0_0000_0028 ; } //hex equivalent of dec 40 

 //added extra bits to make sure, it is the sum that is 40, not the sum after overflow

endclass
 
 initial
    begin
      sum_array c1;
      c1 = new;
      void'(c1.randomize());
      $display("%p",c1.arr);
    end
 
endmodule

I see following output over diff runs
'{'h18,'h8,'h8,'h0}
'{'h0,'h0,h28,'h0}
'{'h0,'h28,'h0,'h0}
'{'h0,'h8,'h20,'h0}