Constrain sum of elements in an array

SystemVerilog
, ,
15

In reply to dave_59:

In reply to naveensv:
Naveen,
I think you meant to declare a dynamic array:

rand bit [2:0] a[];

And you would have to add at least 2 bits to catch the error with the given constraints.
What you are trying to explain is that the result of the array.sum() method only has the precision of the individual array elements. But there is no need to add extra bits to the array, you can use the with clause to cast the elements to a greater width.

a.sum(item) with ( 32'(item) )

Hi Dave,

My requirement is:

  1. array size should be 4
  2. Each element should be divisible by 8
  3. Sum of all elements should be equal to 40

When I run the below code I am getting constraint conflicting error:

module tb;

class sum_array;
   rand int unsigned arr[];

   constraint arr_c { arr.size() == 4;
                      foreach(arr[i]) { (arr[i]%8) == 0; }

   constraint sum_c { arr.sum() with (32'(item)) == 40 ; }
}

endclass

 initial
    begin
      sum_array c1;
      c1 = new;
      void'(c1.randomize());
    end
 
endmodule

Can you please guide me in this regard.

Thank you,

Regards,
Muneeb