Constrain sum of elements in an array

SystemVerilog
, ,
12

In reply to dave_59:

I think i have a similar question. I am using the following code to put constraints on sum of arrays and vector sum of arrays.

I see the following warning and I am trying to see if i can work around this warning.

ncelab: *W,SUMOFL (./testbench.sv,14|32): Constraint expression with unqualified array.sum may overflow.
constraint sum_c { dataq1.sum() < 1000; dataq2.sum() < 1000; }

Dave, Can you explain me how I can fix this warning by casting ?


module tb;
  class c;
    rand logic [7:0] dataq1 [];
    rand logic [7:0] dataq2 [];
    constraint data_size {dataq1.size() == 10; dataq2.size() == 10; }
    constraint data_items { foreach(dataq1[i]) 
                                dataq1[i] < 100;
                            foreach(dataq2[i])
                                dataq2[i] < 50; }
    constraint sum_c { dataq1.sum() < 1000; dataq2.sum() < 1000; }
    constraint sum_product_c {sum_pro() < 100000; }

    function longint sum_pro();
      sum_pro = 0;
      foreach(dataq1[i])
        sum_pro += dataq1[i] * dataq2[i]; 
    endfunction 
    
  endclass
  
  initial
    begin
      c c1;
      c1 = new;
      void'(c1.randomize());
      
      foreach(c1.dataq1[i])
        $display("%0d  %0d", c1.dataq1[i], c1.dataq2[i]);
    end
    
  
endmodule