In reply to dave_59:
The problem becomes that select is not in the m_sub modport list of signals and would not be accessible within the sub module, so how could it pass it down to the module mem?
Somewhere I got in my head that the interpretation of a SystemVerilog modport of an Interface was restricting the visibility (and perhaps adding port direction) of the Interface as a whole, depending on context. The entire Interface is still there, however, in certain context only the modport listed items are available. Passing the modport down to a different modport, well, isn’t clean, but works for Thomas’s original example.
In fact, some of my tools allow such. Others don’t. I’m not sure precisely what the standard says here, I think it’s a unclear.
The alternatives:
- Dont use modports
- Create a new interface within the intermediate level, and pass the appropriate connections through from the modport to the newly created interface. Use this recreated interface to pass down to the next submodule with a different modport
I don’t like 1 as our synthesis tools need hints on port direction - which the modports give. So that leaves 2. For various other reasons, we’ve had to create “interface passthrough” modules which simply pass an interface from one modport to another. This is ugly, but more and more necessary.
I wish this were cleaner in the SystemVerilog standard, and would second Thomas suggestion of adding this to the items to clean up.