In reply to Thomas Kruse:
SystemVerilog interfaces are very poor at handling composition. You cannot say anything kill modport A contains modports B and C. So you either have to use the interface as a whole, or select a particular modport name and stick with it down the hierarchy.
The problem is not just that the directions might not align, but existence of the signals in the modport. For example, suppose I added an extra signal the the m_mem modport that did not exist in any other modport
interface sys_intf();
logic [31:0] addr, data_to_cpu, data_from_cpu, select;
modport m_sub (input data_to_cpu, output data_from_cpu, addr);
modport m_cpu (input data_to_cpu, output data_from_cpu, addr);
modport m_mem (input addr, data_from_cpu, select output data_to_cpu);
endinterface
module sys;
sys_intf sys_inst();
sub sub(.intf_sub(sys_inst.m_sub));
endmodule
The problem becomes that select is not in the m_sub modport list of signals and would not be accessible within the sub module, so how could it pass it down to the module mem?