In reply to chr_sue:
In reply to UVM_LOVE:
You are mixing 2 different constructs.
(1) $cast is a SystemVerilog task/function. This is a language feature.
(2) override is a UVM methodology construct using SystemVerilog.
It would be great to know what your intention is to use $cast an override.
For understanding Override, I was made a simple Override example as the below
module test_module ();
`include "uvm_macros.svh"
import uvm_pkg::*;
class agent_a extends uvm_agent;
`uvm_component_utils(agent_a)
function new(string name = "agent_a", uvm_component parent = null);
super.new(name, parent);
endfunction : new
endclass : agent_a
class agent_b extends agent_a;
`uvm_component_utils(agent_b)
string field = "agent_b.field";
function new(string name = "agent_b", uvm_component parent = null);
super.new(name, parent);
endfunction : new
endclass : agent_b
class agent_c extends uvm_env;
`uvm_component_utils(agent_c)
string field = "agent_c.field";
function new(string name = "agent_c", uvm_component parent = null);
super.new(name, parent);
endfunction : new
endclass : agent_c
agent_a agent_a_h;
initial begin
agent_a::type_id::set_type_override(agent_c::get_type());
factory.print();
agent_a_h = agent_a::type_id::create("agent_a_h", null);
$display("field = ", agent_a_h.field);
end
endmodule : test_module
When I ran the above simulation. I encounter below Error message.
$display("field = ", agent_a_h.field);
|
xmvlog: *E,NOTCLM (testbench.sv,46|39): field is not a class item.
Does UVM Override has also limitation ? I checked https://verificationacademy.com/sessions/inheritance-and-polymorphism
it said that override must have the same prototype.
What does prototype mean?
Does prototype mean that they class must have the relationship between parents and child as $cast?