Configuration Randomization

UVM
,
12

In reply to chr_sue:

In reply to Vignesh_18:
You can have config classes on each hierarchy level. There is no limitation.
You can have a top_config, env_config and several agent_ configs.

Thanks a lot Sir!!

Also, i tried implementing it and i got a following error

Error: (vsim-7073) …/wb_agt/uart_seqs.sv(143): Attempt to dereference null class reference (local::this.r_cfg.lcr) in constraint.

Time: 270 ns Iteration: 5 Process: /uvm_pkg::uvm_sequence_base::start/fork#294_f6a9bf8 File: …/wb_agt/uart_seqs.sv Line: 143

** Error: Assertion error.

Here is the code:
Sequence part

class base_seq extends uvm_sequence#(uart_xtn);

        `uvm_object_utils(base_seq)

        reg_config r_cfg;





        function new(string name="base_seq");
                super.new(name);
        endfunction

endclass
//---------------------------------------------------------FULL DUPLEX----------------------------------------//
class seq1 extends base_seq;

        `uvm_object_utils(seq1)



        function new(string name="seq1");
                        super.new(name);
        endfunction

        virtual task body();
                begin

                        req=uart_xtn::type_id::create("req");

                        if(uvm_config_db#(reg_config)::get(null,"","reg_config",r_cfg))
                                `uvm_fatal("R_CFG","Failed to get()")


                        //------------------------------------------LCR-->DLR REG ACCESS---------------//
                        start_item(req);
                        assert(req.randomize()with{wb_dat_i==8'b1000_0000;wb_we_i==1'b1;wb_addr_i==3;})
                        finish_item(req);

                  //-------------------------------------------DLR_MSB--------------------------//
                        start_item(req);
                        assert(req.randomize()with{wb_dat_i==8'b0000_0000;wb_we_i==1'b1;wb_addr_i==1;})
                        finish_item(req);

   //-------------------------------------------DLR_LSB-------------------------//
                        start_item(req);
                        assert(req.randomize()with{wb_dat_i==8'b0011_0110;wb_we_i==1'b1;wb_addr_i==0;})
                        finish_item(req);

                        //-------------------------------------------LCR-->NORMAL REG ACCESS---------------//
                        start_item(req);
                        assert(req.randomize()with{wb_dat_i[7:2]==0;wb_dat_i[1:0]==r_cfg.lcr;wb_we_i==1'b1;wb_addr_i==3;})
                        finish_item(req);

reg_config class


class reg_config extends uvm_object;

        `uvm_object_utils(reg_config)


        rand bit [1:0] lcr;


        function new(string name="reg_config");
                        super.new(name);
        endfunction
endclass