Config_db - parameters for set/get method

UVM
,
22

In reply to dave_59:

In reply to verif_learner:
There is a mistake here. The first argument to the set/get methods is a context handle. That is an instance of a uvm_component. These methods take the first two arguments and concatenates them together [sv]{ arg1.get_full_name() , arg2 }

. 
Normally arg1 is **this** or **null** depending if you want to specify a relative or absolute path. Only the result of the concatenation matters, not how the original two strings piece together.



Hi Dave,

How can I solve the problem ***"Range width must be constant expression"*** in an assignment like the following, when I get the value of this constant from database?:

``` verilog

data_a = data_b [RDW*i +: RDW];

To make more clear:
In my top test I have a parameter that I receive as a generic from cmd line when I simulate the test:


module test_top #(RDW= 16);
    initial begin
        uvm_config_db #(int)::set(null, "uvm_test_top.*", "RDW", RDW);
    end
endmodule

Then in my scoreboard I have:


int RDW;
function void build_phase (uvm_phase phase);
   void'(uvm_config_db #(int)::get(this, "*", "RDW", RDW));
endfunction

task write ();
   data_a = data_b [RDW*i +: RDW];
endtask

Thank you very much!