In reply to ben@SystemVerilog.us:
Ben ,
I tried both codes :: EDA1 and EDA2 .
For EDA1 , the single ’ ack ’ is considered a Match for ALL 3 antecedents .
[ Q1 ] What if I want an additional check that there Must be 1 ’ ack ’ per ’ req ’ ?
Similarly for EDA2 , the single ’ ack ’ is considered a Match for ALL 3 requests .
[ Q2 ] Similarly I would like to add an additional check that there Must be 1 ’ ack ’ per ’ req ’
So if remaining 2 ’ ack’s ’ aren’t received in both code I should see the assertion Fail twice