Concurrent Assertion b/w 2 signals

SystemVerilog
1

Hi, I have a scenario where when input state_idle is zero then output ip_idle should be zero for next clock. for this i written assertion like below, what i am seeing is assertion was active for one time when state idle becoming 1 to 0 , but i want to check for every time when state_idle is 0, am i missing any condition at antecedent expression

property state_chk;
 (state_idle==0) |=> (ip_idle==0);
endproperty

assert property (@ (posedge clk ) state_chk);
2

The code written matches your description. Please provide a minimal, complete reproducible example.

3

HI Dave, Thanks for reply
May be i was confused with assertion states
When state_idle becoming 1 to 0, i am seeing assertion state moves from inactive to active state and then state moved to finished and stable untill state_idle is 1 , i am seeing during finished state also checked_count is incrementing, so can i assume while during finished state also assertion is in active state ?

4

The way you have written your assertion, every clock cycle state_idle is 0,a new assertion attempt begins and it will pass or fail the next clock cycle. Each assertion attempt is active for 2 clock cycles. If you only care about the case when it goes from 1 to 0, use $fell(state_idle)