Concatenation in `define function in system verilog

SystemVerilog
2

In reply to venkateshla:

There are a couple of typos in the code shown.

In the 4th define, you need to reference size, not size.

There are 3 ``` between _ and s, there should only be 2 ``

There is no need for the 2 at the beginning ofmem

`define mem sram
`define m memory
`define size 1024
`define s `size
 
`define func(mem, s, m) \
    mem``_``s``_``m  // but it is not giving sram_1024_memory, rather it is giving error
 
module name;
    `func(`mem, `s, `m) u_mem(); // this module instantiation.
endmodule
module sram_1024_memory;
  initial $display("%m");
endmodule