Concatenate string and int

SystemVerilog
8

In reply to sh88:

module a ;
int a;
string name;
string name2;

initial
   begin
   a = 5;
   name = "abc";
   // one way
   name2 = $sformatf("%s%0d", name, a);
   $display("a=%d, name1=%s,name2=%s",a,name,name2);
   // another way
   name2.itoa(a);
   name2 = {name,name2};
   $display("a=%d, name1=%s,name2=%s",a,name,name2);
   // yet another way
   $display("a=%d, name1=%s,name2=%s%0d",a,name,name,a);

end
endmodule