Concatenate string and int

SystemVerilog
2

In reply to sh88:

how to concatenate string and int and assigned to a string;
ex:
module a ;
int a=5;
string name=“abc”;
string name2={name,a};
initial
begin
$display(“a=%d, name1=%s,name2=%s”,a,name,name2);
end
endmodule
output:a=5, name1=abc, name2=abc
//i nead the name2 = abc5, but i am getting name2=abc, why it it not working and any other possible way to concatenate?

You can try using $formatf instead, look at the LRM section 21.3.3 Formatting data to a string


module a ;
int a=5;
string name="abc";
string name2;

initial
begin
  name2 = $sformatf("%s%0d", name, a);
$display("a=%d, name1=%s,name2=%s",a,name,name2);
end
endmodule

# KERNEL: a=          5, name1=abc,name2=abc5

Or


module a ;
int a=5;
string name="abc";
string name2 = $sformatf("%s%0d", name, a);

initial
begin
$display("a=%d, name1=%s,name2=%s",a,name,name2);
end
endmodule

# KERNEL: a=          5, name1=abc,name2=abc5

HTH,

-R