Complex FPGA Design verification methodology

UVM
2

In reply to Echotwozero:

  1. At the very least you need top level (system) tests. If the smaller units (schematics) have specifications, or you can infer their specifications from the system specification, then you can test those as needed.

  2. In my opinion VHDL is fine for unit testing, but any verification environment of reasonable complexity should be written in SystemVerilog (or c++).