Common Reg model access for uvm env and virtual seq library

UVM
,
3

In reply to chr_sue:

Hi,

Thanks for quick response but still i did not get the point to resolve this, i have shared some code acrros usage.

class toy_env extends uvm_env;
`uvm_component_utils(toy_env)

extern function new(string name = “toy_env”, uvm_component parent = null);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);

toy_AXIL4_SLAVE_CFG_S_mmap_block_type ral_model; //reg model

// Virtual sequencer to drive commands
toy_gen_virtual_sequencer toy_gen_vseqr;
endclass

function void toy_env::build_phase(uvm_phase phase);
string db_name;
super.build_phase(phase);

ral_model = new({cfg.uvm_db_prefix, "ral_model"});
ral_model.build();
ral_model.default_map.set_base_addr(cfg.ral_base_address);
ral_model.reset();
ral_model.set_hdl_path_root(cfg.hdl_path_root);
ral_model.lock_model();

db_name = "drive_me_ral";
uvm_config_db #(uvm_reg_block)::set(null, "toy_test_top", db_name, ral_model);

**//tried to set this way also**
//uvm_config_db #(toy_AXIL4_SLAVE_CFG_S_mmap_block_type)::set(null, "toy_test_top", db_name, ral_model);

toy_gen_vseqr = toy_gen_virtual_sequencer::type_id::create("toy_gen_vseqr", this);

endfunction : build_phase

function void toy_env::connect_phase(uvm_phase phase);
super.connect_phase(phase);

cfg.drive_ral_model.default_map.set_sequencer(axi_master_agt_s.sqr, ral_model_adapter);
cfg.drive_ral_model.default_map.set_auto_predict(1);

toy_gen_vseqr.axi_s_gen_seqr = axi_master_agt_s.sqr;

endfunction : connect_phase

//package
package toy_gen_seq_pkg;

import uvm_pkg::;
import axi_agent_pkg::;

include "uvm_macros.svh" include “toy.sv” ///reg mmodel

`include “toy_gen_base_s_seq.sv”

`include "toy_gen_virtual_sequencer.sv"
`include "toy_gen_virtual_seq.sv"

endpackage

///// Virtual Sequencer Class
class toy_gen_virtual_sequencer extends uvm_sequencer;
`uvm_component_utils(toy_gen_virtual_sequencer)

uvm_sequencer #(axi_seq_item) axi_s_gen_seqr;
uvm_sequencer #(axi_seq_item) axi_h_gen_seqr;

/// Constructor
function new (string name = “toy_gen_virtual_sequencer”, uvm_component parent);
super.new(name, parent);
endfunction: new

endclass: toy_gen_virtual_sequencer
///// Virtual Sequencer Class ends

///// Virtual Sequence Class
class toy_gen_virtual_seq extends uvm_sequence;

uvm_object_utils(toy_gen_virtual_seq) uvm_declare_p_sequencer(toy_gen_virtual_sequencer)

extern function new(string name=“toy_gen_virtual_seq”);
endclass

task toy_gen_virtual_seq::gen_drive_trans();

toy_gen_base_s_seq s_seq = toy_gen_base_s_seq::type_id::create("s_seq");
s_seq.start(p_sequencer.axi_s_gen_seqr);

endtask : gen_drive_trans
//virtual sequence end

//toy base_s_seq
class toy_gen_base_s_seq extends uvm_sequence#(axi_seq_item);

extern virtual task gen_drive_trans();

toy_AXIL4_SLAVE_CFG_S_mmap_block_type ral_model; ///< Register model

endclass

task toy_gen_base_s_seq::gen_drive_trans();

uvm_reg_block b;
uvm_reg_block reg_model;
axi_master_read_seq rd_seq = axi_master_read_seq::type_id::create("rd_seq");

//config db to get reg blocks
    **//this config db is not working: not getting ral_model**
**//NOT WORKING:** if(!uvm_config_db #(toy_AXIL4_SLAVE_CFG_S_mmap_block_type)::get(null,"toy_test_top", "driver_me_ral",ral_model))

    **//WORKING:**
if(!uvm_config_db #(uvm_reg_block)::get(null,"toy_test_top", "drive_me_ral",ral_model))
	`uvm_fatal(msg_id, "Cannot get() reg_model")

    **//These two methods are not working**
b = reg_model.get_block_by_name("toy"); 
    b.get_reg_by_name("queue_cfg_addr").get_field_by_name("base_addr").write(status, 'h400);

–

//WORKING
rd_seq.read(rc_group_reg[0].get_address(), rcs[0], rresp, m_sequencer, 0, 0, 4);

endtask: gen_drive_trans
//toy base_s_seq ends

//sanity sequence
class toy_sanity_gen_seq extends toy_gen_virtual_seq;

`uvm_object_utils(toy_sanity_gen_seq)

extern function new(string name=“toy_sanity_gen_seq”);

// Body
extern virtual task body();
endclass

function toy_sanity_gen_seq::new(string name=“toy_sanity_gen_seq”);
super.new(name);
endfunction : new

task toy_sanity_gen_seq::body();

toy_top_gen_seq_item toy_top_gen_itm;

repeat(3) begin
toy_top_gen_itm = toy_top_gen_seq_item::type_id::create(“toy_top_gen_itm”);

`uvm_do_on_with(toy_top_gen_itm, CONSTRAINTS); //not fully shown

end

endtask
//sanity sequence end

class test_sanity_gen extends TOY_BASE_TEST; uvm_component_utils(test_sanity_gen)

extern function new(string name=“test_sanity_gen”, uvm_component parent);
extern virtual task main_phase(uvm_phase phase);

endclass

function test_sanity_gen::new(string name=“test_sanity_gen”,uvm_component parent);
super.new(name,parent);
endfunction // new

task test_sanity_gen::main_phase(uvm_phase phase);
uvm_status_e status;

toy_sanity_gen_seq vseq = toy_sanity_gen_seq::type_id::create(“vseq”);

vseq.starting_phase = phase;

phase.raise_objection(this);

//ral model handle is created in base test
ral.toy.queue_config_addr.base_addr.write(status, 'h0000_ffff);

vseq.start(this.tenv.toy_gen_vseqr);
phase.drop_objection(this);

endtask

I am looking to set and get from config_db directly reg_model itself not uvm_reg_block, how to use same ral model in the virtual sequence which is outside of the toy_env(which is using again same ral model…no issues here).

Please suggest.

regards,
nivas