Coding practices in System Verilog

SystemVerilog
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Dear all,
I am getting started with System Verilog. So far I am good with the theoretical concepts. But I want to gain hands on coding experience on system verilog, assertions and coverage. Please suggest me a way to achieve this.
Thanks in advance
-Madhavi

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In reply to MadhaviEerpina:

        Instead of going for best practices at this point,start exploring each section of IEEE System verilog with small examples on your own, if don't understand post that issue in this blog.
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In reply to cool_cake20:

Thanks for your response.It would be a great help for me if you can recommend me any stuff like cook books for system verilog.

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In reply to MadhaviEerpina:

Take a look at papers from

http://sutherland-hdl.com/papers.php

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In reply to ben@SystemVerilog.us:

Thanks ben!

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You can take a look at the post here

Basically you append a character to distinguish between types. There are other similar examples here.