In reply to chr_sue:
In reply to UVM_LOVE:
You have to embed your C++ subroutine into a SV component and connect his component to your UVM environment.
Currently, I can’t afford to embed Reference C++ code as subroutine into a SV component. Because That C++ model is came from another company and they don’t know systemverilog as well.
Do I have to breakdown pure c++ code into SV subroutine? such as by using DPI-C techniques?