In reply to chr_sue:
Hi ,
Need your suggestions in verifying a Moore FSM .
On Sampling signal "a" high on posedge of clock , the State Machine would enter State HIGH_A ( from lets say a Default State ) and drive Output Signal OPA High .
Now this OPA signal could either be Driven through Blocking Assignment ( i.e Combinationally Driven ) or through Non-Blocking Assignment ( i.e Sequentially Driven )
Now my Monitor also Samples signals on posedge of clk . I want to check inside Monitor whether Signal OPA is High or Not ( Error Condition ) on entering State HIGH_A
(a) Am I correct in believing there is a potential race condition between OPA being Driven ( either through Blocking or Non-Blocking Assignment ) and the Monitor Sampling OPA on observing signal “a” high on posedge of clock ?
(b) How could Clocking Blocks be helpful in Sampling OPA correctly ? There is always a possibility that signal a goes low before next posedge of clock , so DUT has entered State HIGH_A and if monitor missed out sampling a High on posedge of clock , it would be left back
(c) One Possibility I see is through #0 input skews which Sample Values in Observed Regions .
But I have read its not a recommended approach although I don’t understand why so ? . It certainly would help my monitor in Sampling Correct Value of OPA Signal in this case
Thanks ,
Himanshu Valecha