Clocking block sampling

SystemVerilog
3

In reply to cgales:
my interface:

interface ram_interface(input bit clk);
  
  logic[4-1 : 0] addr;
  logic[32-1: 0] data;
  logic          cs  ;
  logic          we  ;
  logic          oe  ;
  
  
  clocking cb @(posedge clk);
    
    output #50ps addr,cs,we,oe;
    input #2ps output #50ps data;
  endclocking
  
  modport TB (input clk, clocking cb);
  
endinterface: ram_interface

my monitor:

class ram_monitor extends uvm_monitor;
  `uvm_component_utils(ram_monitor)
  
  function new(name = "ram_monitor", uvm_component parent);
    super.new(name, parent);
  endfunction:new
  
  virtual ram_interface vif;
  ram_seq_item pkt;
  uvm_analysis_port #(ram_seq_item) mon_port;  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(!(uvm_config_db #(virtual ram_interface)::get(this, "*", "intf", vif)))
      `uvm_fatal(get_type_name(), $psprintf("couldn't get an interface"))
      mon_port = new("mon_port", this);
  endfunction:build_phase
  
  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
  endfunction:connect_phase
  
  task run_phase(uvm_phase phase);
    super.run_phase(phase);
    forever begin
      @(vif.cb);
      if(vif.cs == 1 && vif.we == 1)
        begin
          pkt = ram_seq_item::type_id::create("pkt");
          pkt.addr    = vif.addr;
          pkt.data    = vif.data;
          pkt.cs      = vif.cs;
          pkt.we      = vif.we;
          pkt.oe      = vif.oe;
          mon_port.write(pkt);
        end
      if(vif.cs == 1 && vif.oe == 1)
        begin
          pkt = ram_seq_item::type_id::create("pkt");
          pkt.addr = vif.addr;
          pkt.cs   = vif.cs;
          pkt.we   = vif.we;
          pkt.oe   = vif.oe;
          @(vif.cb);
          pkt.data = vif.data; 
          mon_port.write(pkt);          
        end
    end
    
  endtask: run_phase  
endclass:ram_monitor

I mean that pkt.addr = vif.cb.addr is not allowed while in my driver when I drive the DUT using my interface vif.cb.addr <= pkt.addr is allowed.

Thanks!