CLOCK not generating in top

UVM
1

Hi in the below code i am trying to generate the clock but the display present inside the clock generation block is not printing and clock is also not generating due to this my test is hanging, can anyone suggest what might be the issue, in generating the clock, i added the timescale as 1ns/1ns, Thanks in advance.

     initial
        begin
            HCLK=0;
            HRESETn= 0;
            $display("Assignment done"); // printed
        end
initial
    forever
        begin
            #1ns HCLK = ~HCLK;
            $display(" generating clock"); //not printed
        end
    initial 
        begin
            $display("entered loop"); // printed
            repeat(10)@(posedge bus_if.HCLK);
            HRESETn = 1;
            $display("entered loop reset done");// not printed
        end
    assign bus_if.HCLK=HCLK;
    always@(HRESETn) bus_if.HRESETn=HRESETn;
2

This could be due to race conditions, but without an entire example, it is difficult to determine.

It is better to separate functionality into single initial blocks:

interface bus_interface(input HCLK, input HRESETn);
  // other bus signals
endinterface

module testbench();
  bit HCLK, HRESETn;

  bus_interface bus_if(.*);

  initial begin
    HCLK = 0;
    forever #1ns HCLK = ~HCLK;
  end

  initial begin
    HRESETn = 0;
    repeat (10) @(posedge HCLK);
    HRESETn = 1;
  end
endmodule