Clock Frequency Check ( considering Jitter )

SystemVerilog
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5

In reply to dave_59:

For the duty cycle related assertion , similar to the solution to the original question I could use a time literal ::


 //   Duty  Cycle  Must  be  55.555 % +-  0.05 %  for  1MHz  Clock
 
         assert  property( clock_frequency( 555.55ns  , 0.05 * ( 555.55ns ) )

But using a time literal restricts the usage of a generic property .

If the clock period is unknown ( hence can’t use a time literal to the argument(s) ) and I simply want to check the duty cycle , is there any alternative ?