Clock edge is not getting detected inside forever loop

UVM
, ,
8

In reply to mayurkubavat:

I am getting display messages like for example, ‘getting interface’ inside build phase and ‘entered run phase’. I have made run_test and set interface in the same initial block as suggested. No monitor output yet. Could you check if I am raising and dropping objections correctly as shown below:

class ahb_base_seq extends uvm_sequence #(ahb_tx); // created base sequence
	
	`uvm_object_utils(ahb_base_seq);
	
	function new (string name ="");  

		super.new(name); 
		
	endfunction
	
	task pre_body();

		if (starting_phase !=null)

			starting_phase.raise_objection(this);

	endtask

	task post_body();

		if (starting_phase !=null)

			starting_phase.drop_objection(this);

	endtask

endclass

// functional sequence
class ahb_10_tx_seq extends ahb_base_seq;
	
	`uvm_object_utils(ahb_10_tx_seq);

	function new (string name ="");  

		super.new(name); 
		
	endfunction
	
	task body();
		
		super.pre_body(); 
		repeat(10) `uvm_do_with(req,{ req.wr_rd==1'b1; }); 
		super.post_body();

	endtask

endclass