Clock edge is not getting detected inside forever loop

UVM
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6

In reply to rakesh2learn:

Another thought is,

  • You are not using monitor component at all? Add and check for any other display messages. Like, “MON: getting interface”, “MON: Entered run phase” etc. See if you are creating monitor component, and not just compiling!

  • Or run phase is ending immediately, in that case check if you are using objections correctly.

phase.raise_objection(this);
  // Add multiple clock delay
phase.drop_objection(this);
  • It is better to use setting of virtual interface and run_test() in same initial block as it might cause fail to get method because of execution order of initial block.
initial
  begin
    uvm_config_db #(virtual ahb_if)::set(null,"*","phy_intf_var",inf);
    run_test();
end