Clock edge is not getting detected inside forever loop

UVM
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2

In reply to rakesh2learn:

It is possible that the clock ‘hclk’ is not getting generated and is not connected to top level clock.

  • Add a check to see if you are getting interface pointer from configuration database,
if(!uvm_config_db#(virtual ahb_if)::get(this,"","phy_intf_var",vif))
  `uvm_fatal("AHB/MON", "Cannot get virtual interface.");