Checking whether signal is asserted for minimum clock cycles

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

Hi Ben,

I agree with points 2 and 3, which were not thought over by me while coding the assertion.

W.r.t point 1 : If I am using |=> operator, then what if the PORESET_B falls on the next sampling event. There seems no need to change [*0:] to [*1:].

W.r.t point 4 : If $rose(PORESET_B) is true, then it will check (v_t >=32) in the same clock. What is the need of first_match as the consequent is calculated on each sampling event?

Please clarify.