In reply to chr_sue:
In reply to bmorris:
Regarding a reference model you cannot give clear advice to use a SV or any other model. What you are using depends on 2 things. Firstly, what is available. Do system architects have C++ models or is a behavioral model in VHDL or SV available. Or do we have any other reference like a Matlab model. Secondly it has to be a model which represents exactly the function of the DUT. Exactly means in terms of FUNCTION and not of clock cycles (cycle-accurate). Both models can be integrated directly in a UVM testbench using the DPI interface.
In reply to bmorris:
I’m guessing the model needs to care more about FUNCTION, and less about IMPLEMENTATION.
I like bhunter1972’s reply ( predictor / TLM model paradigm - UVM SystemVerilog Discussions - Accellera Systems Initiative Forums ). My only other comment is that aside from using scoreboard one could, in many cases, use assertions.
This is because we’re eventually testing the requirements, and in many cases, assertions with SVA can do that in a mroe readable and executable manner.
I make this point in the following papers:
See my White paper: “Using SVA for scoreboarding and TB designs”
http://SystemVerilog.us/papers/sva4scoreboarding.pdf
and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
available in the verification-horizons October-2013-volume-9-issue-3
http://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3
and “SVA in a UVM Class-based Environment”
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115