Checker for phase of clocks using property

SystemVerilog
8 
realtime t1, t2, half_time_period;

always @(posedge clk1) begin
        t1 = $realtime;
        @(negedge clk1)
        t2 = $realtime - t1;
        half_time_period = t2/2; // half time period of clock 1 divided by 2 to get 90 degree phase shifted time period
end 

property phase_aligned_90_degrees_chk(clk1, clk2, state, realtime half_time_period);
        realtime t1, t2;
        @(posedge clk1) (1, t1=$realtime) ##0 state == 4'h2 |-> @(posedge clk2) (1, t2=$realtime) ##0 ((t2-t1) == half_time_period);
endproperty

I implemented it this way and see a mix of failures and success in the waveform. It’s very confusing, kindly help.