In reply to ben@SystemVerilog.us:
The waveforms clarified the requirements. You can use multiclocking in the assertion. Thus,
ap_aligned: assert property(
@(posedge div_clk_strb) 1'b1 ##0
@(posedge dfe_clk_src) !clk_div1 && !clk_div2 && !clk_div4 ##0
@(negedge dfe_clk_src) clk_div1 && clk_div2 && clk_div4 );
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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October 2013 | Volume 9, Issue 3 | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy