Check signal assert for n cycles where n is configurable

In reply to ben@SystemVerilog.us:

Thanks Ben,

I do not see why v is the one that ends first_match if it is not inside the first_match clause, Is not the local_v local variable the one being modified?

the first_match sentence will last until v goes to 0 or -1.
“…and one cycle later local_v has to be 0.” that is incorrect.


(b, local_v=local_v - 1)[*0] ##1 local_v<=0) // is equivalent to
(local_v)  or //because
// any_seq[*0] ##1 w // is same as w
// any_seq[*0] ##0 w // is a no match 
(b, local_v=local_v - 1)[*1] ##1 local_v<=0) or 
(b, local_v=local_v - 1)[*2] ##1 local_v<=0) or ...

Now, if the dynamic variable is 1, then you have
Thus, If local_v is initially 1,
1<=0) or
(b[*1] ##1 0 <=0) // same as (b ##1 )

Lets say that the local_v value is initially 3, is the following correct?


 (3<=0) or 
 (b[*1] ##1 2<=0) or 
 (b[*2] ##1 1<=0) or 
 (b[*3] ##1 0<=0)  // same as b[*3] ## 1,

My real question here is; when is local_v modified? I mean:


(b, local_v=local_v - 1)[*1] ##1 local_v<=0) or // Is this local_v=local_v - 1 resolved 
(b, local_v=local_v - 1)[*2] ##1 local_v<=0) or //    before this one, and this one before the next one and so for ?