Check signal assert for n cycles where n is configurable

SystemVerilog
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2

In reply to Fpfermoselle:
There are 3 replies:
1) My preferred solution
If the variable used to define the delay has values that are within a constraint range, such as between 0 and 7 (or 15, or at most 32) one can use the generate statement, which appears much simpler than the use of local variables and the sequence_match_item. Example:


generate for (genvar g_i=0; g_i<8; g_i++) begin
  ap_delay_gen: assert property (v==g_i && $rose(a) |-> ##g_i b);
end endgenerate

2) Using tasks
https://verificationacademy.com/forums/systemverilog/paper-understanding-sva-engine-simple-alternate-solutions


string tID="MY_DUT";
int r; 
always @(posedge clk) begin // emulate the firing of assertions
 fork
   t_check_abr();
   // .. t_XXX(); // firing of other emulated properties
 join_none
end

// t_check_abr
//   @ (posedge clk) $rose(a) |-> b[*r] // illegal 
task automatic t_check_abr();
 if($rose(a)) begin : rose_a // attempt succeeds
   repeat(r) begin : rpt 
     if(b) // consequent match
       `uvm_info (tID,$sformatf("%m : t_check_abr PASS, b= %b", b), UVM_LOW)
     else // consequent does not match
        `uvm_error(tID,$sformatf("%m : t_check_abr FAIL @ b= %b", b))
     @(posedge clk);
    end : rpt
  else return; // vacuous pass, antecedent does not match
 end : rose_a
endtask

3) If you MUST use SVA
From my SVA book


11.4.3 Simple repeat (e.g., a[*v]]
ap_repeat_fix: assert property( $rose(a) |-> b[*v] ##1 c);  
p_repeat_equivalent; // /11.4/m5067_gen_options.sv
  int local_v; // this is an internal local variable defined by the tool
  $rose(a) |-> (1, local_v = v)  
               ##0 first_match((b, local_v=local_v - 1)[*0:$] ##1 local_v<=0)
               ##0 c;
endproperty
ap_repeat_equivalent: assert property(p_repeat_equivalent);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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