Check for a signal assertion within a given time window

SystemVerilog
, ,
11

Hi Ben,

Wondering if the above question can be solved with local variables. Please let me know if this can be possible solution:

property ack_cnt;
 int local_var;
 ($rose(ack), loval_var=1) |=> ($rose(ack), local_var = local_var+1)[*9] ##0 (local_var >= 1) && (local_var <= 3) 
endproperty

I am new to assertion. Local variable was first thing that struck.

Thanks