Check data for some range

SystemVerilog
1

Hi All,

I have signal A and B.

A |=> $past(B,n) where n is var. it seems not work, how to fix it? Thanks a lot!

2

You can use a shift register to create a history of B.

 property b_n_cycles_ago;
    logic [MAX_N-1:0] B_hist;
    @(posedge clk) 
    1'b1 |-> (
      // Initialize history
      (B_hist = '0) ##1
      // Shift in B for MAX_N cycles
      (1, B_hist = {B_hist, B})[*MAX_N] ##1
      // Check condition when A is true
      A |-> b_hist[n]
    );
  endproperty
  assert property (b_n_cycles_ago);

Note that n must be bounded by MAX_N.