In reply to pagarwa5:
property p_FSM_A_B_option1;
@(posedge clk) disable iff (!rst)
$rose(state==A) ##1 C==16'H1FFF[->1] ##0 done |=> (state==B, $display(" A - B")) ;
endproperty : p_FSM_A_B_option1
property p_FSM_A_B_option2;
@(posedge clk) disable iff (!rst)
$rose(state==A) ##1 done[->1] |=> (state==B, $display(" A - B")) ;
endproperty : p_FSM_A_B_option2
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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