In reply to birenkumar:
Below hack can help you,
class customized_uvm_reg_hw_reset_seq extends uvm_reg_sequence #(uvm_sequence #(uvm_reg_item));
// Subset of maps to be considered for running this sequence
string test_on_maps[$];
bit [31:0] register_addr;
reg_test_splitter m_reg_split_h;
bit model_should_not_be_reset;
bit predict_retention;
int retention_value;
`uvm_object_utils(customized_uvm_reg_hw_reset_seq)
function new(string name="customized_uvm_reg_hw_reset_seq");
super.new(name);
m_reg_split_h = reg_test_splitter::type_id::create("m_reg_split_h");
endfunction
virtual task body();
uvm_reg regs[$];
uvm_reg_map maps[$];
string map_name;
if (model == null)
begin
`uvm_error("customized_uvm_reg_hw_reset_seq", "Not block or system specified to run sequence on");
return;
end
m_reg_split_h.get_configs();
uvm_report_info("STARTING_SEQ",{"\n\nStarting ",get_name()," sequence...\n"},UVM_LOW);
if (uvm_resource_db#(bit)::get_by_name({"REG::",model.get_full_name()},
"NO_REG_TESTS", 0) != null ||
uvm_resource_db#(bit)::get_by_name({"REG::",model.get_full_name()},
"NO_REG_HW_RESET_TEST", 0) != null )
return;
// Hack for specific model to be reset/not
if(!model_should_not_be_reset)
begin
`uvm_info("RESETTING_REG_MODEL",get_name(),UVM_LOW)
this.reset_blk(model);
model.reset();
end
else
`uvm_info("NOT_RESETTING_REG_MODEL",get_name(),UVM_LOW)
model.get_maps(maps);
// Iterate over all maps defined for the RegModel block
foreach (maps[d])
begin
map_name = maps[d].get_name();
foreach(test_on_maps[i])
begin
if (map_name == test_on_maps[i])
begin
uvm_status_e status;
regs.delete();
maps[d].get_registers(regs);
if (regs.size() == 0)
begin
`uvm_fatal("customized_uvm_reg_hw_reset_seq", "Did not find any registers to test")
return;
end
m_reg_split_h.filter(regs);
foreach (regs[i])
begin :foreach_loop
uvm_reg my_reg = regs[i];
uvm_status_e status;
register_addr = regs[i].get_address();
// Registers with certain attributes are not to be tested
if (uvm_resource_db#(bit)::get_by_name({"REG::",regs[i].get_full_name()},
"NO_REG_TESTS", 0) != null ||
uvm_resource_db#(bit)::get_by_name({"REG::",regs[i].get_full_name()},
"NO_REG_HW_RESET_TEST", 0) != null )
begin
continue;
end
// Simpl hack to load the mirror value apart from reset value
if(predict_retention && regs[i].get_name() == "RETENTION_REGISTER")
regs[i].predict(retention_value);
// Regular mirror method
regs[i].mirror(status, UVM_CHECK, UVM_FRONTDOOR, maps[d], this);
if (status != UVM_IS_OK)
begin : uvm_okay
`uvm_error(get_type_name(),
$sformatf("Status was %s when reading reset value of register \"%s\" through map \"%s\".",
status.name(), regs[i].get_full_name(), maps[d].get_full_name()));
end : uvm_okay
end :foreach_loop
end
end
end
endtask: body
endclass: customized_uvm_reg_hw_reset_seq