Change mirror value of a register field before running uvm_reg_hw_reset_seq

UVM
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16

In reply to birenkumar:

From your environment, you can call like below:

this.regmodel.REGBLOCK.RSTCFG.set_reset(32'h0003);

This would ensure the reset value is updated and when the sequence does reg_model.reset, this would become the mirrored value.