Chained range constraints in SystemVerilog

SystemVerilog
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1

Hi,

I have a question regarding range constraints in SystemVerilog.

Suppose I want to constrain a random variable between 34 and 43. If we try writing:

constraint c3 { 34 <= var1 <= 43;}

Instead of

constraint c3 { var1 >= 34; var1 <= 43;}

constraint c3 { var1 >= 34; var1 <= 43; }

I expected this to generate values only from 34 to 43. However, when I tested it in EDA Playground using VCS, I received values such as:

var1 = 53
var1 = 244
var1 = 102
var1 = 106
var1 = 1

it evaluates it approximately as:

(34 <= var1) <= 43

The first comparison, 34 <= var1, returns either 0 or 1. The second comparison therefore becomes either:

0 <= 43

or:

1 <= 43

Both are true, so the constraint does not actually restrict var1.

Could you please confirm whether my understanding is correct? Also, is there any other reason why chained relational expressions such as 34 <= var1 <= 43 should be avoided in SystemVerilog constraints?

Regards

Sunodh

2

Section 11.2 explains the operator precedence in SystemVerilog. Using the same operator (<=) results in evaluation from left to right, so your understanding is correct.

Constraints are evaluated as boolean expressions which are either 0 or 1, with only the true expressions being valid.

As long as you follow the operator precedence, you can create any expression you desire, but it’s usually better from a code readability standpoint to make simple expressions.

Your best option is to use:

constraint c3 { var1 inside {[34:43]}; }
3

Hi @cgales ,

Thanks for the clarification. I’m aware that inside {[34:43]} is the preferred way.

My main doubt was only about how SystemVerilog evaluates:

34 <= var1 <= 43

Is it exactly treated as (34 <= var1) <= 43, where the first comparison gives 0 or 1, making the second comparison always true?
I just wanted to confirm whether this is the only reason it fails as a range check.

4

Yes. That is how the constraint is evaluated.