vec_pack = 320’( vec_unpack) ; // note ()'s instead of {}'s
works for me, although it does not match the functionality of your for loop. When you declare an unpacked range of [10], that is equivalent to [0:9]. You might want to try:
logic [31:0] vec_unpack [9:0];
Bitstream casts require all bits to be preserved, no padding or truncation. When you do 320’{vec_unpack}, that casts vec_unpack to a packed array of the same size, then it is assigned to another packed array, and standard Verilog rules apply (right justify bits, then pad or truncate).
You may also want to look at the streaming operator to manipulate the bit patterns.
vec_pack={>>32{vec_unpack}};