Can't functions call other functions?

SystemVerilog
, ,
4

In reply to SparkyNZ:
It would help if you learn how to post a minimal reproducible example. Maybe the problem is somewhere else. This code below ran on 4 different tools:

module top;
  bit clk,rxState;
  localparam RX_IDLE = 0;
  
  function void HandleRxIdle;
endfunction
 
function void HandleReceiveStates;
  unique case( rxState )
    RX_IDLE         : HandleRxIdle();
  endcase
endfunction
 
always_ff @( posedge clk )
begin
  HandleReceiveStates();
end
  
initial begin
  #5 clk =1;
  #5 $finish;
end
endmodule