Can we use loops to iterate inside Sequence in Assertion

SystemVerilog
1

//To check duplicates in array below i have my code and i am getting syntax error.
and my doubt is can we iterate using “while” or “for” loop inside sequence?

array = {1, 2, 3, 4, 5, 4, 7, 8, 9, 10};  
sequence check_for_duplicates;
    int i, j;

    // Loop over each pair of elements in the array
    for (i = 0; i < 10; i++) begin
      for (j = i + 1; j < 10; j++) begin
        // Check for duplicates and ensure i is not equal to j to avoid self-comparison
        if (i != j && array[i] == array[j]) 
          disable iff (1) // Disable the sequence when a duplicate is found
            $fatal("Assertion failed: Duplicate values found in the array");
      end
    end
  endsequence
2

You cannot put loops or other procedural code inside a sequence. Sequences are temporal constructs for detecting changes over a period of time. Better would be defining a function and using that in an assertion.

function bit check_for_duplicates(int array[]);
  foreach(array[i])
    foreach(array[j])
      if (i != j && array[i] == array[j] ) return 1;
  return 0;
endfunction

...
assert (!check_for_duplicates(my_array) else $fatal("Assertion failed: Duplicate values found in the array");
3

Hi @dave_59

In above code “return 0” is else part of fareach(array[j]) or foreach(array[i]).

4

Neither. It comes after both foreach loops terminate. Perhaps using begin/end blocks makes it clearer. But they are unnecessary when each block contains only one statement.

function bit check_for_duplicates(int array[]);
  foreach(array[i]) begin : loop_i
    foreach(array[j]) begin : loop_j
      if (i != j && array[i] == array[j] ) return 1;
     end : loop_j
    end : loop_i
  return 0;
endfunction
5

Thank you @dave_59
i have got clear idea about my doubt.