In reply to ben@SystemVerilog.us:
Another option is to use my package at
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
The package includes a tb.
Example
sequence q_dynamic_repeat(q_s, count);
int v=count;
(1, v=count) ##0 first_match((q_s, v=v-1'b1) [*1:$] ##0 v<=0);
endsequence
// in the module
bit clk, a, b, c=1, w;
int d1=2, d2=5;
sequence q_s;
a ##1 c;
endsequence
// ****** DYNAMIC REPEAT q_s[*d1] **********
// Application: $rose(a) |-> q_dynamic_repeat(q_s, d1) ##1 my_sequence;
ap_rpt: assert property(@ (posedge clk)
$rose(a)|-> q_dynamic_repeat(q_s, d1) ##1 my_sequence);
Ben