In reply to Somu:
SystemVerilog macros don’t care about SystemVerilog syntax. Your code needs to make sense after the macro text gets expanded.
A final block is like the inverse of an initial block. It instantiates a block of procedural statements, but is not a statement in itself. A final block executes as the result of a call to $finish. You do not put $finish inside a final block.
There is no need for you to cal $finish because $fatal implicitly calls $finish.