In reply to ben@SystemVerilog.us:
Hi, Ben
I have checked what you provided. It’s not match with my problem. We could see that your assertion is still in the “UVM environment”. What I mean “UVM environment” is all UVM components except DUT.
What I want to check is the assertions existing in DUT. For example, my DUT file has DMA_top.v and DMA_ahb.v. I write assertions about DMA_ahb.v in SVA_checker.sv file and bind them together. How can I check this SVA_checker.sv in DUT under UVM and generate results in report file.