[quote]I want to know that if I add some SVA in the DUT block and doesn’t change the function of design. Can I detect these SVA inside DUT block in UVM environment?[quote]
Yes, this is because the assertions are elaborated at elaboration time (i.e., like modules), not run-time. Assertion statements are illegal in classes. However, see
https://verificationacademy.com/forums/uvm/sva-uvm-class-based-environment-new-paper
I published the following paper in the Feb 2013 edition of the Verification Horizons:
SVA in a UVM Class-based Environment.(page 24)
http://s3.mentor.com/fv/verification-horizons-publication-february-2013.pdf
This article provides an in-depth view of how to apply SystemVerilog assertions (SVA)
to simplify some of the tasks usually done by scoreboards in UVM and also to improve coverage sampling in your testbench. Links to code examples are provided.
Ben Cohen http://www.systemverilog.us/
- SystemVerilog Assertions Handbook, 3rd Edition, 2013
- A Pragmatic Approach to VMM Adoption
- Using PSL/SUGAR … 2nd Edition
- Real Chip Design and Verification
- Cmpt Design by Example
- VHDL books