Can we covergroup inside a monitor

UVM
12

In reply to chr_sue:
hai chr_sue, still its giving an error. here is the complete code of my coverage class


class fifo_coverage extends uvm_subscriber#(fifo_seq_item);
  `uvm_component_utils(fifo_coverage)

fifo_seq_item seq;                  // declaration of seq_item class
virtual sync_interface sync_vintf;  // interface declaration

covergroup sync_fifo_cov;

  WRITE        :coverpoint seq.write iff(!sync_vintf.rst_n) {}
  ALMOST_FULL  :coverpoint seq.almost_full iff(!sync_vintf.rst_n) {}
  FULL         :coverpoint seq.full iff(!sync_vintf.rst_n) {}
  OVERRUN      :coverpoint seq.overrun iff(!sync_vintf.rst_n) {}

  READ         :coverpoint seq.read iff(!sync_vintf.rst_n) {}
  ALMOST_EMPTY :coverpoint seq.almost_empty iff(!sync_vintf.rst_n) {}
  EMPTY        :coverpoint seq.empty iff(!sync_vintf.rst_n) {}
  UNDERRUN     :coverpoint seq.underrun iff(!sync_vintf.rst_n) {} 
endgroup

function new(string name="fifo_coverage", uvm_component parent=null);
   super.new(name,parent);
endfunction:new

function void build_phase(uvm_phase phase);
   super.build_phase(phase);
endfunction:build_phase

virtual function void write(fifo_seq_item pkt);
   seq=pkt;
   sync_fifo_cov.sample();
endfunction

endclass


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*xmvlog: E,CVMNMM fifo_coverage.sv,28|50): Virtual method ‘fifo_coverage::write’ formal argument name does not match base class ‘uvm_subscriber’.