can we bind assertion module to an interface
No. However, you can bind a checker to a SV interface.
Your checker can have assertions (actually, that is the intent).
I describe the 1800’12 checkers in my SVA 3rd edition book.
2)Define the assertions in the class
It is illegal to have concurrent assertions in classes.
Your best bet is to either user the checkers or write the assertions in the interface, or in a module (or checker) bound to t.
Ben Cohen systemverilog.us