Hi Ramuk,
Use the Virtual sequencer concept.In the Virtual sequencer instantiate one common monitor(state monitor). From the UVC Monitor, pass the necessary signals to the state monitor.
Now in the Sequence use the virtual sequencer.
In sequence :
`uvm_declare_p_sequencer(v_sequencer)
if(p_sequencer.state_monitor.signal_name == 1’b1)
//trigger next sequence.
Now to pass the signal name from the uvm monitor to the state monitor.
In UVC monitor:
class uvm_monitor();
uvm_analysis_port #() ap_uvm_monitor;
function new();
ap_uvm_monitor = new();
endfunction
task run_phase();
signal_requred_seq_item seq_item.
seq_item.signal_name_a = a;//(getting from interface)
seq_item.signal_name_b = b;//getting from interface
…
…
ap_uvm_monitor.write(seq_item);
endtask
endclass
IN UVC AGENT:
class uvm_agent;
uvc_monitor mon;
uvm_analysis_port ap_agent;//declare one local analysis port
in connect phase:
monitor.ap_uvc_monitor.connect(ap_agent)
endclass
IN STATE MONITOR:
class state monitor();
uvm_analysis_export ap_export;
bit signal_name_a;
bit signal_name_b;
…
…
function void write(signal t);
this.signal_name_a = t.signal_name_a;
this.signal_name_b = t.signal_name_b;
…
…
endfunction
endclass
IN TOP LEVEL ENV
//instantiate uvc_agent;
//instantiate state_monitor;
in connect phase;
connect uvc agent’s analysis port to state monitors analysis export
Thanks,
-Murali
Thanks,
-Murali