Can i use systemverilog task or function to be called in main() in c program

SystemVerilog
,
3

In reply to Subhra Bera:

thanks for your reply

i was trying what you said ,but i see you made function calls in initial block , is this example intended to be ran using vsim ? if yes then this is not what i meant

i will make my question more clear

here is the .sv file
////////////////////////////////////////////////////////

module data_ex2 ();
export "DPI-C" function Double;
 
function void Double();
  $display("hello from sv");
 
endfunction
endmodule
////////////////////////////////////////////////////////

and now i want to make .c file , and run this task there , i generated the dpiheader.h file
and here is .c file
////////////////////////////////////////////////////////

#include <stdio.h>
#include "dpiheader.h"

extern void Double();

int main (){
	
Double();
return 0 ;
}

////////////////////////////////////////////////////////

and now i will compile it , i want to run the .c file and i am expecting it will print “hello from sv”
////////////////////////////////////////////////////////
gcc main.c
////////////////////////////////////////////////////////
and the output of this that linker says , no refrence for Double()

…
so that is exactly what i want , is this valid or DPI can not do that ?

thank you