Can I pass parameters down

SystemVerilog
, , ,
9

In reply to DavidEllis:

Thanks David. The following code in EDA Playgroud works fine, but got same errors from our env with the similar changes:

Error-[NCEI] Non-constant expression in parameter
[path of bind file]
[RTL module name] [parameter name]
The use of a non-constant expression to override a parameter value is
illegal.
Please replace the offending expression by an elaboration-time constant.


module module_cov #(int ENTRIES, int NUM) (
  input logic [ENTRIES-1:0] rd_q,
  input logic [ENTRIES-1:0] rd_buf [NUM-1:0]
  );
  always_comb
    $display("In module_cov");
endmodule
 
module module_rtl #(parameter ENTRIES = 8, parameter NUM = 2) (
  input logic [ENTRIES-1:0] read_q,
  input logic [ENTRIES-1:0] read_buf [NUM-1:0]
  );
  always_comb
    $display("In module_rtl");
endmodule : module_rtl
 
module top;
  bind module_rtl module_cov #(.ENTRIES(ENTRIES), .NUM(NUM)) module_cov_inst ( // got errors pointing to this line in our env
    .rd_q   (read_q),
    .rd_buf (read_buf)
  );
  always_comb
    $display("In module_top");
endmodule : top