Can I pass parameters down

SystemVerilog
, , ,
4

In reply to ralphkak:

It would help to provide a Short, Self Contained, Correct (Compilable), Example This works for me

interface bind_if #(string PATH) ();
   initial $display("%m %s",PATH);
endinterface
module target;
   parameter string path = "mypath";
   
endmodule : target

module top;
   target t();
   bind target:t bind_if #(.PATH(path)) bt();
endmodule : top